|VHDL design and simulation of a fast beam loss interlock for TTF2|
|A. Hamdi, M. Luong, M. Werner|
The TTF2 fast beam loss interlock provides different modes of protection. Based on the differential beam charge monitoring over a macropulse, a pulse slice or bunch-by-bunch, the signal processing time should be as short as the bunch repetition period (110 ns). The signal delivered by the toroid-like inductive current transformer always shows an envelope droop due to its self-inductance to resistance ratio. When the macropulse length is comparable to this ratio, the charge of each bunch must be derived from the difference of the top to the bottom level on the signal. This necessity combined to the various protection modes leads to a digital implementation. All the processing functionalities are designed with VHDL for a Xilinx FPGA. Because the interlock involves other control signals in addition to the toroid signal with specific shapes, which cannot be easily reproduced for the design validation before the TTF2 completion, VHDL provides meanwhile the possibility for an exhaustive validation of the system with a software test bench including all timing information.