Résumé du preprint DAPNIA-06-641

DAPNIA-06-641
A Multigigahertz Analog Memory with Fast Read-out for the H.E.S.S.-II Front-End
E. Delagnes, F. Feinstein, P. Goret, P. Nayman, J.-P. Tavernet, F. Toussenel, P. Vincent
The H.E.S.S.-I front-end electronics is based on the
ARS0 chip, a multigigahertz sampler and analog memory used as
a level-1 circular buffer. In the future H.E.S.S.-II, the energy
threshold will be decrease as low as 10 GeV. This will require a
much higher acquisition rate capability and a larger dynamic
range incompatible with the electronics developed for HESS-I.
These constraints led to the development of the SAM (for Swift
Analog Memory) chip to replace the ARS0. The SAM chip
includes 2 analog memory channels, with a 256-cell depth each.
The sampling frequency is adjustable up to 2GS/s. Thanks to the
matrix structure of the analog memory, the readout-time of an
event has been decreased by more than two orders of magnitude
compared to the one obtain with the ARS0 chip. It permits to
deal with the high expected rate of H.E.S.S.-II. The SAM input
bandwidth and dynamic range are increased up to 250 MHz and
more than 11 bits respectively.
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