|Design of the ANTARES LCM-DAQ Board Test Bench using a FPGA-based System-on-Chip approach|
|S. Anvar, P. Kestener, H. Le Provost|
System-on-Chip (SoC) design approach consists in using state-of-the-art FPGA devices with embedded RISC processor cores, high-speed differential LVDS links and ready-to-use multi-gigabit transceivers allowing development of compact systems with substantial number of IO channels. Required performances are obtained through a subtle separation of tasks among closely cooperating programmable hardware logic and user-friendly software environment. We report about our experience in using the System-on-Chip (SoC) approach for designing the production test bench of the off-shore readout system for the ANTARES neutrino experiment.