Résumé du preprint DAPNIA-06-597

A Low Power Multi-Channel Single Ramp ADC With up to 3.2 GHz Virtual Clock
E. Delagnes, D. Breton, F. Lugiez, and R. Rahmanifard
During the last decade, ADCs using single ramp architecture have been 
widely used in integrated circuits dedicated to nuclear science 
applications. These types of converters are actually very well suited for 
low power, multi-channel applications. Moreover their wide dynamic range 
and their very good differential non-linearity are perfectly matched to 
spectroscopy measurement. Unfortunately, their use is limited by their long 
conversion time, itself limited by their maximum clock frequency. A new 
architecture is described in this paper. It permits speeding up the 
conversion time of the traditional ramp ADC structures by a factor of 32 
while keeping a low power consumption. Measurement results on a 4-channel, 
12-bit prototype using a 3.2 GHz virtual clock are then presented in 
detail, showing excellent performances of linearity and noise.


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