From 2022 onwards, the upgraded LHCb experiment has switched to a triggerless readout system collecting data at an event rate of 30 MHz and a data rate of 4 Terabytes/second. A software-only High-Level Trigger enables unprecedented flexibility for trigger selections. During the first stage (HLT1), track reconstruction, partial particle identification, and vertex fitting enable a broad and efficient selection process to reduce the event rate to 1 MHz. High multiplicity event reconstruction at 30 MHz represents a significant computing challenge, and LHCb utilizes the inherent parallelism of the triggering process to meet throughput requirements with commercial-grade GPUs. In this seminar, we review this system's software and hardware design, reflect on the challenges of developing and integrating heterogeneous architectures, discuss how it meets LHCb’s performance requirements, and show first commissioning results from LHC Run 3 and prospects for the future.
