CMOS monolithic active pixel sensors or CMOS-MAPS were proposed more than twenty years ago to match the combination of requirements set by a vertex detector at the future ee linear collider. While we are only getting close to this original challenge, an intense R&D brought CMOS-MAPS into performance range unforeseen initially: hit rates exceeding 100 MHz/cm2, time resolutions below the nanosecond or tolerance to fluence beyond 10^15 n_eq/cm2. Consequently, new applications arose, from hadronic colliders to detector in space.
This seminar will start with a reminder on the existing main monolithic pixel sensor series and their characteristics in terms of technology, collection diode, read-out architecture. We will the focus on the future trackers (and vertex detectors) from collider experiments, which have chosen CMOS-MAPS as their baseline and details their specifications: Belle II, LHCb, ALICE 3, EIC, FCCee.
These projects serve as targets for various R&D with different goals and timelines. It is often not representative of the R&D challenge to quote only a single highlight specification like 3 micrometers, 10 picoseconds, GHz/cm2 particle rate, tolerance to fluence up to 1e16 neutron equivalent/cm2 or power dissipation around 10-20 mW/cm2.
In presenting some of the main R&D projects that are proposed within the newly formed DRD3 and DRD7 ECFA/CERN collaborations, we will show that challenges stems also from the interplays between the specifications due to the monolithic nature of the sensor, but also depending on the technology. In particular we will have a closer look at the developement of intrinsic amplification in the silicon and new read-out architectures.
A perspective of developments in France and their global interconnections world-wide will conclude the presentation.
