Test and validation of ANAQIN-X microelectronic chip, for X-rays measurement in space.

Full description

The DEDIP (Department of Electronics, Detectors, and Computing for Physics) and the DAP (Department of Astrophysics) at IRFU (Institute for Research on the Fundamental Laws of the Universe) design readout and data acquisition systems for large-scale space experiments (Solar Orbiter, SVOM, Ariel, etc.). They also develop innovative next-generation sensors as part of R&D programs to revolutionize astrophysical observations for the coming decades.
The intern will join the LISETA (Laboratory for Integration of Electronic Systems for Processing and Acquisition) team within DEDIP, which focuses on developing and testing microelectronic circuits.
The technology developed in our laboratory involves interconnecting a CdTe semiconductor detector, which generates charges via the photoelectric effect, with a segmented microelectronic charge measurement chain consisting of multiple independent pixels.
As part of this work, a matrix readout circuit with 4×3 pixels, each 250×250 µm² in size, was developed during a Ph.D. project. This prototype circuit, called ANAQIN-X, contains twelve pixel architectures that need to be validated to enable the development of a larger-scale circuit (32×32 or 48×48 pixels) for integration into a complete X-ray detection module.

Mission:
To assist in the testing and validation of the circuit, the intern will be tasked with:
-Becoming familiar with the test environment (oscilloscope, integrated circuits to test, signal conditioning and acquisition boards, test scripts).
-Conducting exhaustive tests on noise, amplitude, and power consumption of the circuit:
-Developing automated test scripts in Python.
-Developing scripts to analyse the acquired data.
-Preparing a test report and drawing conclusions about the optimal architecture among the 12 pixels.
-Depending on progress, the student may subsequently contribute to the development of the next circuit, leveraging their testing and measurement experience.

Location

Saclay

Internship conditions

• Internship duration: 3 months
• Level of study: Bac+5
• Training: Master 2
• Continuation in PhD thesis: Yes
• Application deadline: 31 mars 2025

Useful methods and technics:
– Required profile
The candidate is currently in EECS Master 1 (or equivalent) specialised in microelectronic design or electronics and search for a 3-6 month internship.
Scientific and technical required competences are:
o Working principle and modelisation of MOS transistors
o Analog electronics knowledge :
 Amplifiers – Charge sensitive amplifiers
o Digital electronics knowledge
 FPGA-Microcontrollers
 Serial interface (SPI, I2C)
o Signal processing basis
 Filters theory
 Signal to noise ratio
o Bonus: Knowledge even partial on the Cadence Virtuoso design suite :
 Microelectronic schematic design
 Layout design
 Electrical simulation (SPICE – Spectre)
 Design rules check and Layout Versus Schematic (ASSURA – Calibre)
Knowledge on semiconductor physics and microelectronic processing will be considered as a bonus.
Aside these technical competences, candidate will be curious, dynamic and eager to propose personal solutions.

Computer languages and software:
Python, analyse des données, bonus : microélectroniques (Cadence)

Supervisor

BAUDIN David
Phone: +33 1 69 08 36 47
Email :

Head of the laboratory DEDIP / LISETA

DE LA BROISE Xavier
Phone: +33 1 69 08 40 93