Design and characterization of CMOS circuits for Applications in Quantum Engineering

Design and characterization of CMOS circuits for Applications in Quantum Engineering

11/19/2019
Types d’événements
Séminaires d’Instrumentation
Bat 141, salle André Berthelot (143) Masque recommandé
Visio @132.167.216.81
80 places
Vidéo Projecteur
11/19/2019
from 1:15 PM at 2:30 PM

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Quantum bits consisting of single electron or hole spins are realized at CEA-Grenoble on 300mm-wafer industrially compatible CMOS technology.

Their spin state can be manipulated and read-out to build, one-day, a quantum processor. While semiconductor technologies might allow the fabrication of the required thousands of quantum-bits, it also opens valuable possibilities for integrated electronics along with the quantum processor, allowing for better qubit control and higher speed.

We will present cryogenic circuits designed and tested at CEA-LETI/IRIG using the newly-developed Fully Depleted Silicon-On-Insulator 28nm CMOS technology at temperatures as low as 50mK.

CEA-Leti/IRIG